Conventional semiconductor electronic memory devices of the EPROM or FLASH EPROM type are constructed in the form of cell matrices divided into sections that are essentially sub-matrices formed of memory cell blocks having predetermined dimensions. Each block has bias and address lines to select the individual memory cells and decode the information contained therein. Such a semiconductor memory device is described in Applicant's European Patent No. 0 573 728.
In particular, this patent discloses a process for making an integrated device of the EPROM or FLASH-EPROM type in which the individual memory blocks include a cell matrix made up of a plurality of mutually orthogonal word lines and bit lines. The cross points of the word lines and bit lines define the memory cells. This type of structure is known in the art as a "tablecloth" or cross point matrix, and is peculiar in that the bit lines are formed on the semiconductor substrate by parallel, continuous diffused stripes. The metal contacts are only formed at the opposite ends of the bit lines and provide termination pads for each of the memory blocks. Thus, there are few metal contacts in the area of the integrated memory cells, so the capacity for integration on semiconductor substrate is greatly expanded.
A circuit diagram of this basic configuration is shown in FIG. 1. As shown, opposite contact regions 4 border the floating gate memory cells 3. Each memory cell 3 is bounded by a corresponding continuous main bit line 7, and a discontinuous bit line or bit line "segment" 17. Each segment is connected to an adjacent continuous bit line through an address active clement 20, and there are right and left address active elements 20 for each bit line segment.
Additionally, FLASH memory cells require field oxide isolation areas in order to maintain a high capacitive ratio between the control gate and the floating gate. However, the field oxide occupies much of the circuit area of the semiconductor substrate. Considering the particular instances of EPROMs (which are erased by UV radiation) and OTP memories (which cannot be erased), a high capacitive ratio between the control gate and the floating gate appears to be overkill and adds to the overall dimensions of the integrated circuit. Thus, there is a need for an organizational structure for the memory cells that retains the matrix configuration yet enables the circuit area occupied by the matrix to be greatly reduced.